The apparatus of the present invention generally relates to data processing systems and more particularly to data processing operations provided over a common input/output bus.
In a system having a plurality of devices coupled over a common bus an orderly system must be provided by which bidirectional transfer of information may be provided between such devices. This problem becomes more complicated when such devices include for example one or more data processors, one or more memory units and various types of peripheral devices, such as magnetic tape storage devices, disk storage devices, card reading equipment, and the like.
Various methods and apparatus are known in the prior art for interconnecting such a system. Such prior art systems range from those having common data bus paths to those which have special paths between various devices. Such systems also may include a capability for either synchronous or asynchronous operation in combination with the bus type. Some of such systems, independent of the manner in which such devices are connected or operate, require the central processor's control of any such data transfer on the bus even though for example the transfer may be between devices other than the central processor. In addition, such systems normally include various parity checking apparatus, priority schemes and interrupt structures. One such structural scheme is shown in U.S. Pat. No. 3,866,181. Another is shown in U.S. Pat. No. 3,676,860. A data processing system utilizing a common bus is shown in U.S. Pat. No. 3,815,099. The manner in which addressing is provided in such systems as well as the manner in which for example any one of the devices may control the data transfer is dependent upon the implementation of the system, i.e., whether there is a common bus, whether the operation thereof is synchronous or asynchronous, etc. The system's response and throughput capability is greatly dependent on these various structures.
A particular structural scheme is shown in U.S. Pat. Nos. 3,993,981, 3,995,258, 3,997,896, 4,000,485, 4,001,790 and 4,030,075 which describe an asynchronously operated common bus. The present invention is an improvement thereon in which the system throughput capabilities are improved by allowing a device on the common data bus to request that another device on the common data bus provide the requesting device with multiple words of information. The multiple word request is made in a single bus cycle and the requested information is to be provided in a series of responding bus cycles. The present invention further provides for the requesting device to make a multiple word request of the other device without regard for whether the other unit is capable of a multiple fetch operation. This permits systems to be built in which the requesting device makes multiple fetch requests and the responding devices can be either multiple fetch or nonmultiple fetch devices or a mixture of both. This increases system throughput by providing for multiple fetch operations whenever possible without requiring prior knowledge on the part of the requesting unit. Further, by providing logic in the requesting unit to allow it to adapt to the number of words of information actually transferred by the responding device, logic is not required in the responding unit to recover from abnormal conditions in which less than the number of words of information requested can be provided. System throughput is also increased by providing logic in the requesting device to allow it to utilize the words of information as they are transferred by the responding device without requiring that the requesting device wait until the last word of information is transferred.
It is accordingly a primary objective of the present invention to provide an improved system having a plurality of devices connected to a common bus in a manner that permits a requesting device to make a multiple fetch request for information of another device connected to the common bus without regard for whether the other device is a nonmultiple fetch device, multiple fetch device, or a multiple fetch device that cannot retrieve all the words of information requested in the multiple fetch request.